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 Intel® Centrino™ Mobile Technology Support Information

 

Intel® Centrino™ Mobile Technology

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Support resources are provided by Intel to ensure the latest technical information and driver updates are available for systems based on Intel® Centrino™ mobile technology. This information is supplemental to the documentation and resources provided by your notebook manufacturer.

Support information common to all components within the Intel Centrino brand can be found directly on this site. For detailed component information, please refer to the following resources:
bullet Intel® PRO/Wireless 2100 LAN MiniPCI Adapters        
bullet Intel® Pentium® M processor
bullet Intel® 855 Chipset Family
Battery life and specifically power management of the Intel® Centrino™  system can be optimized via hardware, software, or firmware. These elements work together to balance power usage and performance for a notebook system.

Many elements required to extend battery life are implemented directly into the processor, chipset, and wireless components of Intel® Centrino™ Mobile Technology. Power is conserved through the following hardware features and technologies:

bulletMicro-Ops Fusion: 10% fewer Micro-Ops resulting in faster execution at lower power.
bulletDedicated Stack Manager: Greater than 5% fewer Micro-Ops. The processor employs sophisticated hardware control for stack management and implements a synchronization mechanism to eliminate power hungry micro-ops.
bulletPower-Optimized Processor System Bus: The Intel Pentium® M processor has the lowest PSB voltage ever! Lower power from low voltage and fewer pins results in more de-powering capability.
bulletDynamic core frequency switching (100/133/200 MHz ):
bulletOptimized internal clock gating for 3D and display engines: Another low power feature where we do not clock the 3D or display engines unless they are required. This lowers chipset power.
bulletDynamic I/O buffer disabling for Intel Centrino Mobile Technology PSB/Mem: Dynamic Buffer disabling for both Processor System Bus and memory intelligently reduces signaling on these interfaces resulting in lower chipset power consumption.

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Copyright © 2003 John Proulx All Rights Reserved
Last modified: 01/16/08

 
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